In the manufacture of semiconductor integrated circuits, (IC's), in particular of 16 Mb DRAM chips, polysilicon straps are extensively used. In each elementary memory cell, a polysilicon strap allows an electrical contact between the drain region of the active NFET device and one electrode of the storage capacitor. As far as the specific steps of the polysilicon strap fabrication are concerned, a conventional fabrication process basically includes nine basic steps after the gate conductor (GC) stack/TEOS SiO.sub.2 spacer formation has been completed in the GC module.
These nine steps consist of: (1) depositing a blanket layer of silicon nitride onto the structure that will be subsequently used as a hard mask for the boron ion implantation and out diffusion steps, (2) delineating a photomask (PS mask) over said silicon nitride layer according to the desired pattern, (3) etching exposed portions of the silicon nitride layer and the TEOS SiO.sub.2 plug also referred to as the TTO (Top Trench Oxide) plug in order to expose the silicon substrate at the NFET device drain location and the portion of the doped polysilicon fill to be used as the capacitor contact electrode and then stripping the photo mask, (4) implanting boron dopants into the silicon substrate and doped polysilicon fill exposed areas, (5) conformally depositing a layer of undoped polysilicon material onto the wafer, (6) out diffusing boron dopants from implanted polysilicon and silicon into said undoped polysilicon layer to produce a doped portion to be subsequently used as the polysilicon strap, (7) removing the portions of the polysilicon layer that remain undoped with a selective KOH wet process, (8) oxidizing the said doped polysilicon strap portion, and (9) finally removing the silicon nitride hard mask. All these processing steps are conducted in the polysilicon strap (PS) module. After these nine steps have been completed, each storage capacitor is connected to the drain of its corresponding NFET device to provide the desired elementary memory cell.
FIG. 1 schematically illustrates a structure which is a part of a wafer once the gate conductor stack/TEOS SiO.sub.2 spacer has been completed in the GC module. Structure 10 basically consists of a silicon substrate 11 with a gate conductor stack 12 formed thereon. The stack is comprised of a bottom 125 nm thermal SiO.sub.2 layer (not shown), a 200 nm thick gate polysilicon layer 13, a 170 nm thick tungsten silicide (WSi.sub.2) layer 14 and a 400 nm thick TEOS SiO.sub.2 cap 15. A 120 nm thick TEOS SiO.sub.2 spacer 16 coats the sides of the stack. The storage capacitor is formed in a "deep trench" referenced 17 which is filled with polysilicon material. The lower portion is filled with undoped polysilicon 18 and the upper portion is filled with doped polysilicon 18'. The undoped polysilicon fill referenced 18 is only isolated from silicon substrate 11 by a classic ONO (Oxide/Nitride/Oxide) layer 19 while the doped polysilicon fill 18' is isolated therefrom by said ONO layer 19 and a TEOS SiO.sub.2 collar 20. A TEOS SiO.sub.2 plug 21 is formed atop the doped polysilicon fill 18'. The structure of FIG. 1 results of a number of processing steps to which the bare silicon wafer has been submitted to and which are briefly summarized hereunder.
First of all, a Si.sub.3 N.sub.4 layer (referred to as the Si.sub.3 N.sub.4 pad layer no longer visible in FIG. 1) is deposited onto the bare silicon substrate 11 then patterned to delineate the areas to be etched. Next, deep trenches 17 are formed in the substrate by dry etching. The ONO layer 19 is formed on the trench sidewalls and bottom. The ONO coated trenches are filled with undoped polysilicon. During a step referred to as the "recess 1" etch step, about 2.5 .mu.m of undoped polysilicon are removed from the trench in a plasma etcher. The TEOS SiO.sub.2 collar layer 20 is conformally deposited onto the structure 10 and is an isotropically etched to leave only the portion on the sides of the trench which is referred to as the collar 20. Next, a step of blanket depositing a layer of doped polysilicon is performed and the structure is planarized to leave the doped polysilicon fill 18'. Finally, a determined amount of the doped polysilicon fill 18' is removed to form a recess. The height difference between the silicon substrate 11 surface and the top of the remaining doped polysilicon fill 18' is referred to herein below as the "recess 2" depth X. The target is to have a value of X as close as possible of a nominal value X0=160 nm. This step of forming the "recess 2" terminates the operations conducted in the so-called deep trench (DT) module. Now, shallow isolation trenches are formed in the so-called shallow trench isolation (STI) module which includes a chem-mech polishing step. The TEOS SiO.sub.2 plug 21 is formed at this stage of the process. It is highly desired to have the thickness Y of said TEOS SiO.sub.2 plug 21 close to a theoretical nominal value given by Y0=X0=160 nm, to exactly fill the "recess 2" produced in the DT module. The fabrication continues in the gate conductor (GC) module to achieve said gate conductor stack/TEOS SiO.sub.2 spacer formation. The specific processing steps that are now required to build the polysilicon strap between the NFET device drain and the doped polysilicon fill 18' forming one electrode of the storage capacitor at the PS module level will be now described by reference to FIGS. 2 to 9.
First, the structure 10 of FIG. 1 is coated with a 26.5 nm conformal layer 22 of silicon nitride as shown in FIG. 2 to form a hard mask for subsequent boron ion implantation and out diffusion steps. Now turning to FIG. 3, a layer 23 of a photosensitive material is deposited onto the structure 10. An adequate material is the photoresist labelled IP3250 commercially sold by TOKYO-OHKA, Tokyo, Japan which is deposited with a thickness of about 1.1 .mu.m. After deposition, the photoresist layer 23 is exposed, then baked and developed as standard to leave a patterned layer forming photo mask 23 also referred to as the PS mask. Its role is to define the strap position at the surface of the silicon substrate 11, but as apparent from FIG. 3, a portion of the layer 22 situated above the gate stack and a spacer 16 is also exposed. This is required to overcome overlay problems due to the lithographic equipment.
The process continues with the BOSS/MTTO (Boron Out diffused Silicon Strap/Masked Top Trench Oxide) etching step. To that end, the wafer is placed in a plasma reactor such as an AME 5000, a MERIE plasma etcher manufactured by Applied Materials Inc, Santa Clara, Calif., USA, and etched with an appropriate CHF.sub.3 /CF.sub.4 /Ar chemistry to expose the doped polysilicon fill 18'. The etching mixture attacks the exposed portions of the silicon nitride layer 22 and underlying SiO.sub.2 layers, i.e., the cap TEOS SiO.sub.2 layer 15 and TEOS SiO.sub.2 plug 21. After this etching step, resist photo mask 23 is stripped and boron ions are implanted. Areas of the silicon substrate 11 and of the doped polysilicon fill 18' that are not protected by the silicon nitride layer 22 are doped. At this stage of the process, the structure 10 is illustrated in FIG. 4 which in particular shows the specific areas of the structure 10 that have been implanted. As apparent from FIG. 4, the drain of the NFET and the capacitor electrode to be connected therewith that are formed during the out diffusion step are identified by letters D and E respectively. This etching step is the most critical step of the PS module because it is performed with a fixed time which is only determined by the TEOS SiO.sub.2 cap 15 and SiO.sub.2 spacer 16 thicknesses. Therefore, a first important parameter is the maximum TEOS SiO.sub.2 cap 15 thickness W that is permitted to be etched. In that respect, arrow referenced CP1 designates the critical point of this step. No further thinning of the SiO.sub.2 spacer 16 that laterally protects the gate conductor 14 can be accepted beyond this point. To obtain good final yields it is essential that the tungsten silicide forming layer 14 will not be subsequently exposed. Parameters W, X and Y are shown in FIG. 4.
As apparent from FIG. 5, structure 10 is now conformally coated with a 100 nm thick undoped polysilicon layer 24. Then, structure 10 is heated to produce the out-diffusion of boron atoms from the silicon substrate 11 and polysilicon fill 18' into the portion of the undoped polysilicon layer 24 that is in contact therewith. In FIG. 6, a plurality of small arrows illustrates this out-diffusion effect and the boundaries of the doped portion of polysilicon layer 24 identified by numeral 24' are also shown therein. The remaining undoped polysilicon portions of layer 24 are eliminated by dipping the wafer in a KOH bath (selective wet process). As a result, only the doped portion of the polysilicon layer 24' forming the polysilicon strap remains above the structure 10 as depicted in FIG. 7.
In the PS module, a thin 21 nm thick SiO.sub.2 layer 25 is thermally grown on the polysilicon strap 24' surface as shown in FIG. 8. After removal of the unprotected portions of the silicon nitride layer 22, the resulting final structure is shown in FIG. 9.
The conventional fabrication process continues with the formation of electrical contacts (personalization) in the back end of the line (BEOL) as standard.
As far as the polysilicon strap integrity is concerned, typical defects that can be observed when the above mentioned conventional fabrication process is employed are illustrated in FIGS. 10 and 11.
Now turning to FIG. 10(A), there is shown a good strap 24' that is obtained when "recess 2" depth X has the nominal value X0. If the "recess 2" depth is higher than the nominal value, an "open" strap is produced as apparent from FIG. 10(B) because the presence of a remaining portion of the SiO.sub.2 plug 21, there is no access to the doped polysilicon fill 18'. Now, if the "recess 2" depth is lower than the nominal value, FIG. 10(C) shows that in this case, there is a short between the two adjacent straps 24'-1 and 24'-2.
Now turning to FIG. 11(A), there is shown the top portion of a deep trench 17 wherein the thickness of the TEOS SiO.sub.2 plug 21 (parameter Y) has the nominal value Y0. In this case, after the dry etching step of FIG. 4 has been performed, the doped polysilicon fill 18' is correctly exposed, which in turn produces a good polysilicon strap 24'. If the TEOS SiO.sub.2 plug 21 is too thick, because said dry etching is performed during a fixed time, the polysilicon strap 24' does not contact the doped polysilicon fill 18', leading to an "open" strap visible in FIG. 11(B). On the contrary, if the TEOS SiO.sub.2 plug 21 is too thin, a short appears between the two polysilicon straps 24'-1 and 24'-2 as illustrated in FIG. 11(C).
In the above polysilicon strap fabrication process, the BOSS/MTTO dry etching step to expose the polysilicon fill 18' described by reference to FIG. 4 is therefore the most critical, mainly because this by-time etching step is limited by the TEOS SiO.sub.2 cap 15 thickness W (and the SiO.sub.2 spacer 16 thickness as well). If the BOSS/MTTO etching step is too long, both cap and spacer can be completely etched. When exposed to steam during the subsequent step of forming the SiO.sub.2 layer 25, the tungsten silicide of the gate conductor 14 has a natural tendency to swell, thus leading to the destruction of the gate conductor stack 12. On the contrary, if it is too short, there is a serious risk that said fill 18' not be exposed. The etching time is a function of the TEOS SiO.sub.2 plug thickness Y which in turn is related to the "recess 2" depth X. The measurement of depth X performed at the end of the "recess 2" etch step (at the DT module level) takes into account the thickness of the Si.sub.3 N.sub.4 pad layer. Unfortunately this thickness is not uniform over the whole surface of a wafer (and from wafer to wafer of a same lot). The measurement is therefore inaccurate and moreover it is made outside the plasma etcher and not above the active area where the polysilicon straps are fabricated.